In the manufacturing procedure of integrated circuits, the specifications are determined, and designing is performed according to the specification, after having examined carefully if anything has been overlooked. FIG. 11 is a flowchart of the procedure for designing integrated circuits. First, the specification of an Application Specific Integrated Circuit (ASIC) is obtained from the product specification (step g1). Circuit architecture is then studied (step g2). Circuit designing is then performed based on the study of the circuit architecture (step g3). This circuit designing is performed while performing logic verification (step g4).
After circuit designing, logic synthesis of the circuit is performed (step g5). Next, layout expansion is performed based on the logic synthesis (step g6). At this stage, the circuit design is complete. When the circuit is designed, the circuit is manufactured (step g7), and a real machine is evaluated by using the produced circuit (step g8). In the above sequence, the present invention is related to the logic synthesis at step g5.
In the development of integrated circuits, a circuit architecture study for studying a function to be realized using the specification as an input, and studying the circuit configuration for realizing the function is executed in the following flow. Normally, in the development of the integrated circuits, functions for realizing a product are extracted without omission from the product specification, and a study of a circuit configuration for realizing the dug up functions and a macro study such as Intellectual Property (IP) are executed. Macro here refers to the one including the IP that can be used without changing a RAM, a ROM, or the like.
Initial estimate for a circuit for which the configuration has been studied, and the size of the IP to be realized is performed, by calculating the number of gates if known at this stage, and if the number of gates is not known, the number of flip-flops is calculated from the required number of signals and the time required for the processing, to estimate the size to be realized. A plurality of functions is grouped to form one block, based on the estimated size and the number of input/output signals (hereinafter, “ports”) for the respective functions. This grouping is performed for all functions.
In the logic design, a circuit is designed for a programmable logic device by a means such as Hardware Description Language (HDL) based on the functions and the estimated size, to perform on-board function evaluation. After having finished the evaluation, redesign and reevaluation are performed at the time of forming the ASIC.
After completion of the function evaluation, when cost reduction is realized by forming the ASIC, designing taking the ASIC into consideration is not normally performed at the time of designing the programmable logic device (for example, FPGA). Therefore, redesign is required for the ASIC based on the design data of the programmable logic device, due to differences between the ASIC and the programmable logic device, like a macro such as an I/O buffer, a device test circuit, and a memory. This results in problems such as double management of design data due to redesign, prolonged development period and an increase in the development cost due to redesign and reevaluation of functions.
The ASIC has a feature of prolonged development period but low cost, and in contrast, the programmable logic device (FPGA) has a feature of short development period but high cost.
The present invention has been made in consideration of the above problems, and it is an object of the present invention to provide a development method of integrated circuits, to which a method of creating a netlist between blocks as port connection information from port information of blocks obtained by functionally dividing a chip and port information of the chips (disclosed in Japanese Patent Application Laid-Open No. 2000-90142) is applied, in the circuit architecture study applied for logic design, logic synthesis, and concurrent (parallel) development of a layout in the development of a large-scale ASIC, and an apparatus that controls a logic synthesis tool so that blocks constituting the integrated circuit to be developed by the development method of the integrated circuits and a net between blocks are formed in an optional size and optional number from the netlist between blocks. It is further an object of the present invention to realize a common architecture, and provide a development method of integrated circuits that can avoid redesign and re-verification as much as possible, and a program storage medium for storing the development method of the integrated circuits.
Recently, even an ASIC with 10 M gates or more have been developed by microfabrication of a semiconductor. However, with the electronic equipment becoming high-function and complicated, implementation design for performing specification design, logic design, floor plan, logic synthesis, layout design, and timing verification requires long time and it becomes difficult to ensure the design quality. Particularly, remake of the ASIC development not only extends the development period of electronic equipment, but also increases cost and a loss of market investment opportunity.
Therefore, a programmable logic device having a short development turn around time (TAT) and an easy-to-change design is used in many occasions, but the programmable logic device is expensive, and its downsizing is difficult. Accordingly, in many occasions, functions are realized first by the programmable logic device, and after debugging by prototyping, the ASICs are formed at the time of mass-production.
However, even if verification is performed by prototyping of the programmable logic device with the assumption of forming the ASIC, there is a problem in the serial development from the programmable logic device to the ASIC in that it is difficult to shorten the entire development process. Particularly, when a timing problem occurs in the implementation design at the time of developing the ASIC, there is the possibility that redesign of the programmable logic device must be performed again. Consigning the design to outside the company, such as a semiconductor vendor, causes an increase in the cost as well as in human resources in the consignee.
Further, when redesign takes place exclusively in the ASIC due to a difference in the structure between the programmable logic device and the ASIC device, not only does debugging by the programmable logic device become meaningless, but also the development period is prolonged to thereby cause a cost increase. In either case, it causes a loss of market investment opportunity.
As a measure against the prolonged development period accompanying a large scale ASIC, as disclosed in Japanese Patent Application Laid-Open No. 2000-90142, circuit architecture study, logic design and verification, and implementation design are concurrently performed. However, specification design, logic design and verification are prolonged due to complicated functions of the electronic equipment and fast market movement, and hence it becomes difficult to shorten the development process. Further, when the development is executed concurrently, human resources having the knowledge of ASIC development and a development tool are necessary, thereby causing a problem in that training about the development tool, which becomes complicated with the progress of the semiconductor technology, becomes necessary.
Therefore, it is also an object of the present invention to provide a concurrent development system, a concurrent development program, and a concurrent development method of the ASIC and the programmable logic device, which enable seamless and concurrent development of the ASIC and the programmable logic device, ensure the design quality while reducing the development period, and can reduce human resources and cost required for the development.